1. Field of Invention
The present invention relates to a flash memory cell. More particularly, the present invention relates to a NAND memory cell at an initializing state and a process for initializing a NAND memory cell.
2. Description of Related Art
As electronic technologies continue to improve, all types of information products including but not limited to the desktop computer, notebook computer and personal digital assistant (PDA), have been developed. Flash memory device has superior multi-access characteristics, including write, read, and erase, whereas data is retained in the cell even when power is off. Therefore, flash memory has become a broadly used non-volatile memory device for personal computers and electronics appliances.
Moreover, the popular flash memory array that is broadly used by the industry includes NOR gate array structure and NAND array structure. Since the memory cells in NAND array structure are connected, it is more integrated than the NOR array structure. Generally speaking, in a NAND array structure, programming and erasing operations are via +Vg F-N (Fowler-Nordheim) and −Vg FN tunneling effect for 1-bit/cell applications, respectively. We proposed an initializing NAND memory operation that is suitable for 2-bits/cell applications. The 2-bits/cell operation is performed with CHE (channel-hot-electron) program and +Vg FN erase methods. The initializing process can reduce the 2nd-bit effect of 2-bits/cell applications.